Simple 4T static ram cell for low power CMOS applications

ABSTRACT

An SRAM memory cell device comprises wordline and bitline inputs for enabling read/write access to memory cell contents, and, a diffusion region for maintaining a voltage to preserve memory cell content when the cell is not being accessed. The device further comprises a transistor device having a gate input for receiving a wordline voltage to turn off the transistor device when not performing memory cell read/write access; and, a gate oxide layer formed under the transistor device gate exhibiting resistance property for leaking current therethrough when the wordline voltage is applied to the gate input and the transistor device is off. The diffusion region receives voltage derived from the wordline voltage applied to said gate input to enable retention of said memory cell content in the absence of applied bitline voltage to thereby reduce power consumption.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to semiconductor devices, and morespecifically, to an improved 4T static RAM cell for low power CMOSapplications.

2. Discussion of the Prior Art

FIG. 1(a) illustrates a schematic of a 4T SRAM cell 10 according to theprior art. In the prior art SRAM cell 10, a PFET transistor 15 operatingunder control of the wordline (W/L) conducts the bitline voltage to theinternal node 18 of the cell comprising NFET transistor 20 a, 20 b in across-coupled latch configuration. That is, when the W/L gate goes lowfor read applications, the low internal node within the cell pulls oneof the two bitlines low through the W/L device and pull-downtransistors, e.g., 15 and 20 a. When writing data, the bitline (B/L)voltage is conducted to the internal nodes 18, 19. Operations regardingwriting and reading of data are well known to skilled artisans. It isthe case that, in the prior art 4T SRAM cell 10, the bit linesadditionally function to remain high (except in write or readapplications) to allow each PFETs to act as a resistor by virtue of theleakage current (I_(off) leakage) provided by the PFET 15 when turnedoff (wordline is high). That is, the voltage at the internal node 18 ismaintained by the high B/L when PFET 15 is turned off. In view of FIG.1(a), it is understood that one of the internal nodes is going to behigh 18, the other internal node will be low 19 and that constituteseither a logic one (1) or zero (0) depending on the predetermined designconvention. The device of FIG. 1(a) is described in greater detail in areference entitled “A 1.9 μm² Loadless CMOS Four-Transistor SRAM Cell ina 0.18-μm Logic Technology” to K. Noda, K. Matsui, et al. I.E.D.M. 1998,pp. 643-646 which illustrates how the 4T cell may be designed where theinternal node can be pulled up by the off current leakage of thewordline PFET only when the bit lines B/L are kept precharged high. Therequirement that all the array B/Ls remain high for maintaining thestate of the 4T SRAM cell is undesirable for low power CMOSapplications. FIG. 5(a) is a further schematic depiction of the priorart 4T SRAM cell of FIG. 1(a) which illustrates the reliance on PFETI_(off) resistances R1 and R2 from the B/L's precharged to a highvoltage to the internal nodes 18 and 19.

It would thus be highly desirable to provide a 4T SRAM cell that doesnot require the bitline to remain at a high level, thus enablingreduction of power consumption requirements for the SRAM cell.

It would further be highly desirable to provide a 4T SRAM cell having aPFET gate oxide layer connecting the wordline that exhibits a resistanceproperty when a wordline (W/L) voltage is applied, the gate oxide layerconducting leakage current for biasing an internal node of the SRAM cellin order to maintain the static cell contents.

Furthermore, it would be highly desirable to implement in a CMOS circuitgenerally, a gate oxide layer that exhibits a temperature independentresistance property for use in circuit applications.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide in CMOS circuitsgenerally a gate oxide layer that exhibits a nearly temperatureindependent resistance property. Specifically, the gate oxide layer isbiased to provide a quantum tunneling leakage current that isproportional to the bias voltage applied and the thickness of the oxidelayer. The amount of leakage, e.g., in picoamperes/per unit area is themeasure of resistance and is proportional to the gate oxide layerthickness.

Advantageously, utilizing such a gate leakage current property, thevoltage of the internal node of the 4T SRAM cell of FIG. 1 may bederived from the wordline which, for the majority of time, is alwaysheld high. Consequently, the bitline voltages may be kept low or atVdd/2, which significantly reduces power consumption of the SRAM arrayin operation. Additionally, there will be a reduced chance of readdisturbance associated with fluctuations in the B/L voltages.

It is contemplated that other CMOS devices may exploit the resistiveproperty provided by such gate oxide layers.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features, aspects and advantages of the apparatus and methods ofthe present invention will become better understood with regard to thefollowing description, appended claims, and accompanying drawings where:

FIG. 1(a) is a prior art schematic diagram illustrating a 4T SRAM cell.

FIG. 1(b) is a schematic diagram illustrating the 4T SRAM cell accordingto the invention.

FIG. 2 is a graph of the gate leakage property versus gate oxidethickness for various levels of bias voltage.

FIG. 3 illustrates the construction of a portion of the 4T SRAM cell 10of FIG. 1.

FIG. 4(a) illustrates one method for forming the lower resistance regionof the gate oxide layer 35 of FIG. 3 to the desired thickness.

FIG. 4(b) illustrates a second method for forming the lower resistanceregion of the gate oxide layer 35 of FIG. 3 to the desired thickness.

FIGS. 4(c) (1)-4(c) (4) illustrate a third method for forming the lowerresistance region of the gate oxide layer 35 of FIG. 3 to the desiredthickness.

FIG. 5(a) is a further schematic depiction of the prior art 4T SRAM cellcorresponding to FIG. 1(a).

FIG. 5(b) is a further schematic depiction of the 4T SRAM cell of theinvention corresponding to FIG. 1(b).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 is a graph 100 of the gate leakage property versus gate oxidethickness for various levels of oxide layer bias voltage. In accordancewith this graph, via a carefully fabricated gate oxide layer and appliedbias voltage, a desired leakage current, e.g., in picoamperes/per unitarea, may be effected. The gate oxide layer, besides functioning as adielectric, particularly exhibits quantum mechanical tunneling phenomenawhen a bias is applied to function as a constant resistance device. Byvirtue of the quantum mechanical tunneling phenomena, it is the casethat the resistance value is largely temperature independent.

According to the invention, the 4T SRAM device 10′ of FIG. 1(b) isfabricated with such a gate oxide layer that exploits this principle.Particularly, as will be described in greater detail, the wordlinepolysilicon PFET structure of the device 10′ is fabricated with asuitably thin underlying gate oxide layer, for example, in accordancewith the graph characteristics of FIG. 2. That is, beneath the W/Lpolysilicon layer, a gate oxide layer may be formed such that, with thesuitable bias derived from the wordline W/L (which, as mentioned, isgenerally maintained at a high level), enables the internal node 18′ toretain a high voltage independent of the bitline B/L state. This isdesirable, because, in contrast to the prior art, the bitline may now bemaintained at a lower state or even float, which results in less powerconsumption. FIG. 5(b) is a further schematic depiction of the 4T SRAMcell of the invention corresponding to FIG. 1(b) which illustrates thereliance of gate oxide resistances R1′ and R2′ for biasing the internalnodes 18′, 19′ with a voltage derived from the worldline voltage(normally held high).

FIG. 3 is a detailed diagram illustrating the construction of a portion30 of the 4T SRAM cell 10′ of FIG. 1(b). As shown in FIG. 3, thewordline device are PFET devices. According to the invention, anunderlying gate oxide layer overlaps the diffusion region on theinternal node side of the device and, that may be tailored to have somespecified leakage in accordance with the graph of FIG. 2. Thus, forexample the gate current may be calculated in accordance with thefollowing equation:

Ig=2E13_(e) ^((−1.1*tox))

where tox is the gate oxide layer thickness in Angstroms (Å) and Ig=gatecurrent in pA/μm² at a 1.0 Volt bias.

As shown in FIG. 3, the W/L p+ polysilicon layer comprising PFET 15′with isolation spacer elements 31 a,b formed therein includes anunderlying gate oxide layer 35 ranging anywhere from about 1.0 Å-30.0 Åin thickness, and in accordance with current manufacturing techniquesabout 10.0 Å-20.0 Å in thickness. The SRAM cell portion 30 shown in FIG.3 further includes a PFET diffusion region, e.g., p+ region layer 38,which connects to a diffusion region, e.g., n+ diffusion region 40,forming the internal node 18′. According to the invention, the expectedgate oxide leakage to the internal node is formed through an overlapregion 45. That is, in accordance with the principles of the invention,a portion of the gate oxide layer 35 functions as a resistor element sothat, with W/L bias voltage (e.g., about 0.8-2.5 volts) applied to PFET15′, leakage current results through overlap region 45 from the wordlineto the diffusion 38. It should be understood that for thinner oxidelayer, thermionic emission phenomena may contribute to the resultingleakage current. This leakage current restores the diffusion region 38to the high state within the cell and obviates the need for the bit linevoltage to supply current in any way to that internal node i.e., thereis no current going through the bit line according to the invention.

FIG. 4(a) illustrates one method for forming a portion of the gate oxidelayer 35 of FIG. 3 to the desired thickness or degree of conductivity.In the device of FIG. 4(a) there is an underlying Si region 32 having apatterned oxide layer 35. Particularly, there is grown an initial layerof sidewall oxide 42 a,b surrounding the W/L gate and a nitride (Si₃N₄)layer 44 is applied, patterned and etched. Then, more sidewall oxide isgrown on the outside to accumulate in thickness where the nitride hasbeen etched away. In an alternative embodiment, the nitride layer 44 maybe applied first, then patterned and etched before growing the sidewalloxide layers. It is known that the silicon nitride Si₃N₄ preventsoxidation from occurring where it remains. In each case, “bird'sbeaking” (thickening of oxide) at the corner 35 a is prevented thusenabling increased leakage at corner 35 a, i.e., the quantum mechanical(QM) tunneling will take place to the desired extent. Since the oxidelayer is thicker at gate corner 35 b, QM gate tunneling is prevented atthat corner.

As further shown in FIG. 4(b), the oxide “resistor” region is formed byblock level and implant to increase the gate leakage at this locationor, by dual gate methods (FIG. 4(c)) where the W/L PFET gate oxide isintentionally thinner than the grounded source NFET in the cell. Thisworks because the N-well region 32 is maintained at the same potentialas the W/L except during read/write operations where the W/L is broughtlow. Therefor, the gate oxide thickness across the entire channel may bebrought uniformly thin and the function is preserved.

The second method illustrated in FIG. 4(b), is to open up a region atthat corner 35 a where leakage current is desired with a conventionalmask and implant Si or Ge or some inert material (etc. Argon) in theopened region to enhance the tunneling through the oxide, i.e., damagethe sidewall oxide layer 42 a and induce more leakage at that corner 35a. Preferably, given the gate oxide layer over the W/L poly, angledimplants are performed to damage the oxide so that corner 35 a would bethe one that would leak.

A third method is a dual gate method where a thicker gate oxide is firstgrown to a thickness of about 35 Angstroms to 50 Angstroms, i.e., enoughwhere there is not any significant oxide tunneling. Then, a mask iscovered and exposed to open up certain regions, like at the corner ofthe gate where leakage is desired or the entire channel region of theW/L PFET. With the opening in the resist, the oxide is then removed,i.e., stripped down to the underlying silicon. Then, at the cornerregion, the resist is stripped and the oxide is regrown to the desiredthickness, e.g., 10-20 Å. Then the gate is formed, i.e., polysiliconregion is formed and patterned, and the process continues. This methodis advantageous if the gate poly can be realigned to the same specificarea where the opening was formed.

FIG. 4(c) (1) illustrates a first step of the dual gate method forforming the low resistance portion of the SRAM device. In FIG. 4(c) (1)the process includes forming one or more isolation trench regions 53 andexpose the Si regions between the isolation trenches to grow a thickeroxide layers 51 a, . . . ,51 d. In FIG. 4(c) (2), NFET regions 55 arethen patterned in the cell, and the PFET regions, e.g., region 56, areexposed. Further the oxide at regions 56 are removed, for example by anHF containing solution. The next step (not shown) involves stripping theresist and forming the thin oxide in the PFET W/L region, and furtherdepositing the polysilicon and patterning. The results of these stepsare shown in FIG. 4(c) (3) which depicts the formation of the NFETdevices 55′ and the PFET device 15′ and illustrates the thin gate oxidelayer 35 and the spacers 31 a and 31 b as shown in greater detail inFIG. 4(c) (4). As shown in FIG. 4(c) (4), the NFET devices 55′ areformed in a thick oxide region 65 whereas the PFETS are formed in thethin oxide region 35. It is understood that the dual gate oxidemethodology depicted in FIGS. 4(c) (1)-4(c) (4) are formed using a blockmask and skilled artisans may avail themselves of several methods forforming two or more regions of the different gate oxide thickness.

While the invention has been particularly shown and described withrespect to illustrative and preformed embodiments thereof, it will beunderstood by those skilled in the art that the foregoing and otherchanges in form and details may be made therein without departing fromthe spirit and scope of the invention which should be limited only bythe scope of the appended claims.

Having thus described our invention, what we claim as new, and desire tosecure by Letters Patent is:
 1. A SRAM memory cell device, havingwordline and bitline inputs for enabling read/write access to memorycell contents, and, including a diffusion region for maintaining avoltage to preserve memory cell content when said cell is not accessed,said device comprising: a transistor device having a gate input forreceiving a wordline voltage to turn off said transistor device when notperforming memory cell read/write access; and, a gate oxide layer formedunder said transistor device gate exhibiting resistance property fortransmitting current therethrough when said wordline voltage is appliedto said gate input and said transistor device is off, wherein saiddiffusion region receives voltage derived from said wordline voltageapplied to said gate input to enable preservation of said memory cellcontent in the absence of applied bitline voltage to thereby reducepower consumption; wherein said resistance property is a result of aquantum mechanical tunneling effect in said gate oxide layer; wherein athickness of said gate oxide layer determines an amount of leakagecurrent; and wherein said gate oxide thickness ranges from about 1angstrom to 30 angstroms.
 2. The SRAM memory cell device as claimed inclaim 1, wherein said resistance property is temperature independent. 3.The SRAM memory cell device as claimed in claim 1, wherein an amount ofapplied voltage to said gate input determines an amount of leakagecurrent.